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description the cxp85840a/85848a/85856a are the cmos 8-bit microcomputer integrating on a single chip an a/d converter, serial interface, timer/counter, time-base timer, closed caption decoder, data slicer, on-screen display function, i 2 c bus interface, pwm output, remote control reception circuit, hsync counter and watchdog timer, besides the basic configurations of 8-bit cpu, rom, ram, i/o ports. the cxp85840a/85848a/85856a also provide a power-on reset function and sleep function that enables to lower the power consumption. features a wide instruction set (213 instructions) which covers various types of data ?16-bit operation/multiplication and division/boolean bit operation instructions minimum instruction cycle 333ns at 12mhz operation incorporated rom 40k bytes (cxp85840a) 48k bytes (cxp85848a) 56k bytes (cxp85856a) incorporated ram 2176 bytes (excludes closed caption decoder and vram for on-screen display) peripheral functions ?a/d converter 8-bit 6-channel successive approximation method (conversion time of 26.7s at 12mhz) ?serial interface 8-bit clock sync type, 1 channel ?timer 8-bit timer 8-bit timer/counter 19-bit time-base timer ?closed caption decoder data slicer corresponds to fcc (eds supported), 8 13 dots, 192 character types 15 character colors, 4 lines 34 characters frame background 15 colors/ half blanking italic, underline, vertical scrolling ?on-screen display (osd) function 12 16 dots, 192 character types, 15 character colors 2 lines 24 characters frame background 8 colors/ half blanking background on full screen 15 colors/ half blanking edging and vertical scrolling for every line jitter elimination circuit sprite osd, 12 16 dots, 1 screen, 8 colors for every dot ?i 2 c bus interface ?pwm output 8 bits, 8 channels ?remote control reception circuit 8-bit pulse measurement counter, 6-stage fifo ?hsync counter 2 channels ?watchdog timer interruption 15 factors, 15 vectors, multi-interruption possible standby mode sleep package 64-pin plastic sdip/qfp piggyback/evaluator cxp85890a 64-pin ceramic psdip (supports custom font) perchase of sony's i 2 c components conveys a licence under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specifications as defined by philips. ?1 cxp85840a/85848a/85856a e97739a86 cmos 8-bit single chip microcomputer sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. 64 pin sdip (plastic) 64 pin qfp (plastic) structure silicon gate cmos ic
? 2 cxp85840a/85848a/85856a v i n x l c e x l c r g b i y s y m h s y n c v s y n c s i s o s c k e c t o r m c h s c 0 h s c 1 a n 0 t o a n 5 c v s s c v d d c a p l f c 2 d a t a s l i c e r c c d e c o d e r o n s c r e e n d i s p l a y s e r i a l i n t e r f a c e u n i t 8 b i t t i m e r / c o u n t e r 0 r e m o c o n h s y n c c o u n t e r 0 h s y n c c o u n t e r 1 a / d c o n v e r t e r f i f o 3 2 i n t 2 i n t 1 i n t 0 s c l 1 s c l 0 s d a 1 s d a 0 i 2 c b u s i n t e r f a c e u n i t 8 b i t p w m w a t c h d o g t i m e r p r e s c a l e r / t i m e b a s e t i m e r s p c 7 0 0 c p u c o r e r o m 4 0 k / 4 8 k / 5 6 k b y t e s c l o c k g e n e r a t o r / s y s t e m c o n t r o l r a m 2 1 7 6 b y t e s v s s v d d m p r s t x t a l e x t a l p w m 0 t o p w m 7 p o r t a p a 0 t o p a 7 8 p b 0 t o p b 6 7 p c 0 t o p c 7 8 p d 0 t o p d 7 8 p e 0 t o p e 2 3 p f 0 t o p f 7 8 i n t e r r u p t c o n t r o l l e r p o r t b p o r t c p o r t d p o r t e p o r t f 8 b i t t i m e r 1 2 l f c 1 8 6 block diagram
? 3 cxp85840a/85848a/85856a 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 3 6 4 6 1 6 2 p c 3 p c 2 p c 1 p c 0 e c / p d 7 r m c / p d 6 h s 1 / p d 5 h s 0 / p d 4 s i / p d 3 s o / p d 2 s c k / p d 1 i n t 2 / p d 0 h s y n c / p a 7 v s y n c / p a 6 r s t v s s x t a l e x t a l p a 5 / a n 5 p a 4 / a n 4 p a 3 / a n 3 p a 2 / a n 2 p a 1 / a n 1 p a 0 / a n 0 c v s s l f c 2 l f c 1 v i n c v d d c a p i n t 1 / p b 6 p b 5 p c 4 p c 5 p c 6 p c 7 p f 0 / p w m 0 p f 1 / p w m 1 p f 2 / p w m 2 p f 3 / p w m 3 p f 4 / s c l 0 / p w m 4 p f 5 / s c l 1 / p w m 5 p f 6 / s d a 0 / p w m 6 p f 7 / s d a 1 / p w m 7 p e 0 / t o p e 1 p e 2 / i n t 0 m p v s s v d d n c e x l c x l c y m y s i b g r p b 0 p b 1 p b 2 p b 3 p b 4 note) 1. nc (pin 46) is always connected to v dd . 2. vss (pins 16 and 48) are both connected to gnd. 3. mp (pin 49) is always connected to gnd. pin assignment (top view) 64-pin sdip
? 4 cxp85840a/85848a/85856a note) 1. nc (pin 40) is always connected to v dd . 2. vss (pins 10 and 42) are both connected to gnd. 3. mp (pin 43) is always connected to gnd. h s 1 / p d 5 h s 0 / p d 4 s i / p d 3 s o / p d 2 s c k / p d 1 i n t 2 / p d 0 h s y n c / p a 7 v s y n c / p a 6 r s t v s s x t a l e x t a l p a 5 / a n 5 p a 4 / a n 4 p a 3 / a n 3 p a 2 / a n 2 p a 1 / a n 1 p a 0 / a n 0 c v s s 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 1 p f 3 / p w m 3 p f 4 / s c l 0 / p w m 4 p f 5 / s c l 1 / p w m 5 p f 6 / s d a 0 / p w m 6 p f 7 / s d a 1 / p w m 7 p e 0 / t o p e 1 p e 2 / i n t 0 m p v s s v d d n c e x l c x l c y m y s i b g 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 p d 6 / r m c p d 7 / e c p c 0 p c 1 p c 2 p c 3 p c 4 p c 5 p c 6 p c 7 p f 0 / p w m 0 p f 1 / p w m 1 p f 2 / p w m 2 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 3 6 4 6 1 6 2 l f c 2 l f c 1 v i n c v d d c a p i n t 1 / p b 6 p b 5 p b 4 p b 3 p b 2 p b 1 p b 0 r 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 pin assignment (top view) 64-pin qfp
? 5 cxp85840a/85848a/85856a (port a) 8-bit i/o port. i/o can be set in a unit of single bits. (8 pins) (port b) 7-bit i/o port. i/o can be set in a unit of single bits. (7 pins) (port c) 8-bit i/o port. i/o can be set in a unit of single bits. (8 pins) (port d) 8-bit i/o port. i/o can be set in a unit of single bits. can drive 12ma synk current. (8 pins) (port e) 3-bit i/o port. i/o can be set in a unit of single bits. (3 pins) (port f) 8-bit output port and large current (12ma) n-channel open drain output. lower 4 bits are medium drive voltage (12v); upper 4 bits are 5v drive. (8 pins) 6-bit osd display output. (6 pins) pin description symbol pa0/an0 to pa5/an5 pa6/vsync pa7/hsync pb0 to pb5 pb6/int1 pc0 to pc7 pd0/int2 pd1/sck pd2/so pd3/si pd4/hs0 pd5/hs1 pd6/rmc pd7/ec pe0/to pe1 pe2/int0 pf0/pwm0 to pf3/pwm3 pf4/scl0/pwm4 pf5/scl1/pwm5 pf6/sda0/pwm6 pf7/sda1/pwm7 r, g, b, i, ys, ym i/o/ analog input i/o/input i/o/input i/o i/o/input i/o i/o/input i/o/i/o i/o/output i/o/input i/o/input i/o/input i/o/input i/o/input i/o/output i/o i/o/input output/output output/i/o output/i/o output i/o description analog inputs to a/d converter. (6 pins) osd display vertical sync signal input. osd display horizontal sync signal input. external interruption request input. active at the falling edge. external interruption request input. active at the falling edge. serial clock i/o. serial data output. serial data input. hsync counter (ch0) input. hsync counter (ch1) input. remote control reception circuit input. external event input for timer/counter. rectangular wave output for timer/counter external interruption request input. active at the falling edge. 8-bit pwm output. (8 pins) i 2 c bus interface transfer clock i/o. (2 pins) i 2 c bus interface transfer data i/o. (2 pins)
? 6 cxp85840a/85848a/85856a symbol exlc xlc vin cap lfc1, lfc2 cv dd cvss extal xtal rst mp nc v dd vss input output input input output i/o input osd display clock oscillation i/o. oscillation frequency is determined by the external l and c. external composite video signal input. input the 2vp-p signal via a capacitor. connects a data slicer capacitor between cap and cvss. connects a low-pass filter capacitor for pll circuit between lfc1 and lfc2. positive power supply for data slicer. gnd for data slicer. connects a crystal for system clock oscillation. when a clock is supplied externally, input it to extal and leave xtal open. system reset; active at lo w le vel. i/o pin. outputs a low level when the power is turned on and the internal power-on reset function operates. (mask option) test mode pin. always connect to gnd. no connected. under normal operation, connect to v dd . positive power supply. gnd. connect two vss pins to gnd. i/o description
? 7 cxp85840a/85848a/85856a d a t a b u s r d ( p o r t a ) a a i p 0 w h e n r e s e t v s y n c , h s y n c i n p u t p o l a r i t y 0 w h e n r e s e t s c h m i t t i n p u t p o r t a d a t a p o r t a d i r e c t i o n p o r t a d a t a p o r t a d i r e c t i o n d a t a b u s a / d c o n v e r t e r r d ( p o r t a ) p o r t a f u n c t i o n s e l e c t i o n 0 w h e n r e s e t a a i p i n p u t m u l t i p l e x e r 0 w h e n r e s e t i n p u t p r o t e c t i o n c i r c u i t p o r t s b , c d a t a d a t a b u s r d ( p o r t s b , c ) a a i p i n t 1 p o r t s b , c d i r e c t i o n 0 w h e n r e s e t s c h m i t t i n p u t input/output circuit formats for pins port a port a port b port c 2 pins 6 pins 15 pins hi-z hi-z hi-z pin when reset circuit format pa0/an0 to pa5/an5 pb0 to pb5 pb6/int1 pc0 to pc7 pa6/vsync pa7/hsync
? 8 cxp85840a/85848a/85856a p o r t d d a t a p o r t d d i r e c t i o n d a t a b u s r d ( p o r t d ) i n t 2 , s i , h s 0 , h s 1 , r m c , e c * l a r g e c u r r e n t 1 2 m a a a i p s c h m i t t i n p u t 0 w h e n r e s e t * p o r t d d a t a p o r t d d i r e c t i o n d a t a b u s r d ( p o r t d ) s c k o n l y * l a r g e c u r r e n t 1 2 m a s c k , s o s e r i a l o u t p u t e n a b l e s c h m i t t i n p u t a a i p * 0 w h e n r e s e t p o r t e f u n c t i o n s e l e c t i o n d a t a b u s r d ( p o r t e ) i n t 0 t o p o r t e d i r e c t i o n p o r t e d a t a s c h m i t t i n p u t o n l y f o r p e 2 a a a a i p 1 w h e n r e s e t 1 w h e n r e s e t f o r p e 0 a n d 1 1 w h e n r e s e t f o r p e 0 a n d 1 0 w h e n r e s e t f o r p e 2 port d port d port e 6 pins 2 pins 3 pins hi-z hi-z pe0, pe1: high level pe2: hi-z pd1/sck pd2/so pe0/to pe1 pe2/int0 pd0/int2 pd3/si pd4/hs0 pd5/hs1 pd6/rmc pd7/ec pin when reset circuit format
? 9 cxp85840a/85848a/85856a p o r t f d a t a p o r t f f u n c t i o n s e l e c t i o n s c l , s d a 1 w h e n r e s e t 0 w h e n r e s e t * i 2 c o u t p u t e n a b l e p w m 4 t o p w m 7 b u s s w t o o t h e r i 2 c p i n s ( s c l 1 f o r s c l 0 ) * l a r g e c u r r e n t 1 2 m a s c l , s d a ( i 2 c c i r c u i t ) s c h m i t t i n p u t a a i p p o r t f d a t a p o r t f f u n c t i o n s e l e c t i o n p w m 0 t o p w m 3 * 1 2 v d r i v e v o l t a g e l a r g e c u r r e n t 1 2 m a 1 w h e n r e s e t 0 w h e n r e s e t * port f port f 4 pins 4 pins 6 pins 2 pins pf4/pwm4/scl0 pf5/pwm5/scl1 pf6/pwm6/sda0 pf7/pwm7/sda1 hi-z hi-z hi-z oscillation halted r g b i ys ym pf0/pwm0 to pf3/pwm3 exlc xlc a a r , g , b , i , y s , y m w r i t i n g d a t a t o o u t p u t p o l a r i t y r e g i s t e r b r i n g s o u t p u t t o a c t i v e . a a a a a a a a o u t p u t p o l a r i t y 0 w h e n r e s e t o s c i l l a t i o n c o n t r o l a a a a e x l c a a a a a a a a i p o s c d i s p l a y c l o c k a a i p x l c pin when reset circuit format
? 10 cxp85840a/85848a/85856a 2 pins 1 pin rst oscillation low level extal xtal a a a a a a i p a a a a e x t a l x t a l d i a g r a m s h o w s t h e c i r c u i t c o m p o s i t i o n d u r i n g o s c i l l a t i o n . f e e d b a c k r e s i s t o r i s r e m o v e d d u r i n g s t o p m o d e . ( t h i s d e v i c e d o e s n o t e n t e r t h e s t o p m o d e . ) a a a a s c h m i t t i n p u t p u l l - u p r e s i s t o r f r o m p o w e r - o n r e s e t c i r c u i t ( m a s k o p t i o n ) m a s k o p t i o n o p pin when reset circuit format
? 11 cxp85840a/85848a/85856a * 1 v in and v out should not exceed v dd + 0.3v. * 2 the large current output port is port d (pd) and port f (pf). note) usage exceeding absolute maximum ratings may permanently impair the lsi. normal operation should be conducted under the recommended operating conditions. exceeding those conditions may adversely affect the reliability of the lsi. v dd v in v out v outp i oh i oh i ol i olc i ol topr tstg p d ?.3 to +7.0 ?.3 to +7.0 * 1 ?.3 to +7.0 * 1 ?.3 to +15.0 ? ?0 15 20 100 ?0 to +75 ?5 to +150 1000 600 v v v v ma ma ma ma ma c c mw mw pf0 to pf3 pins total of all output pins ports excluding large current outputs (value per pin) large current output ports (value per pin * 2 ) total of all output pins sdip-64p-01 gfp-64p-l01 item symbol ratings unit remarks absolute maximum ratings (vss = 0v reference) supply voltage data slicer supply voltage high level input voltage low level input voltage operating temperature 5.5 5.5 5.5 5.5 v dd v dd v dd + 0.3 0.3v dd 0.2v dd 0.4 +75 v v v v v v v v v v c item symbol min. max. unit remarks 4.5 3.5 2.5 4.5 0.7v dd 0.8v dd v dd ?0.4 0 0 ?.3 ?0 cv dd v ih v ihs v ihex v il v ils v ilex topr guaranteed operation range for 1/2 and 1/4 frequency dividing clocks guaranteed operation range for 1/16 frequency dividing clock or sleep mode guaranteed data hold range for stop mode * 1 * 5 * 2 * 3 extal pin * 4 * 2 * 3 extal pin * 4 v dd * 1 this device does not enter the stop mode. * 2 pa, pb, pc, pe0 to pe1, scl0 to 1, sda0 to 1 pins. * 3 int2, sck, so, si, hs0, hs1, rmc, ec, int1, hsync, vsync, rst pins. * 4 specifies only during external clock input. * 5 cv dd and v dd should be set to the same voltage. recommended operating conditions (vss = 0v reference) supply voltage input voltage output voltage medium drive output voltage high level output current high level total output current low level output current low level total output current operating temperature storage temperature allowable power dissipation
? 12 cxp85840a/85848a/85856a v dd = 4.5v, i oh = ?.5ma v dd = 4.5v, i oh = ?.2ma v dd = 4.5v, i ol = 1.8ma v dd = 4.5v, i ol = 3.6ma v dd = 4.5v, i ol = 3.0ma v dd = 4.5v, i ol = 4.0ma v dd = 5.5v, v ih = 5.5v v dd = 5.5v, v il = 0.4v v dd = 4.5v, i ol = 12.0ma high level output voltage low level output voltage input current i/o leakage current open drain i/o leakage current (in n-ch tr off state) i 2 c bus switch connection impedance (in output tr off state) supply current input capacitance 4.0 3.5 37 2.5 5.0 10 5 10.0 20 a ma pf 50 10 120 50 ma ma a a 0.4 0.6 1.5 0.4 0.6 40 ?0 ?00 10 v v v v v a a a a 0.5 ?.5 ?.5 v v pa to pd, pe r, g, b, i, ys, ym pa to pd, pe r, g, b, i, ys, ym, pf0 to pf3, rst * 1 pd, pf pf4 to pf7 (scl0, scl1, sda0, sda1) extal rst * 2 pa to pe, hsync, vsync, r, g, b, i, ys, ym, rst * 2 pf0 to pf3 pf4 to pf7 scl0: scl1 sda0: sda1 v dd = 5.5v, v il = 0.4v v dd = 5.5v, v i = 0, 5.5v v dd = 5.5v, v oh = 12.0v v dd = 5.5v, v oh = 5.5v v dd = 4.5v v scl0 = v scl1 = 2.25v v sda0 = v sda1 = 2.25v v dd * 3 cv dd stop mode * 4 v dd = 5.5v, termination of 12mhz oscillation sleep mode v dd = 5.5v, 12mhz crystal oscillation (c 1 = c 2 = 15pf) pa to pe, scl, sda, exlc, extal, vin, rst clock 1mhz 0v for no-measured pins item symbol pins conditions min. typ. max. unit v oh v ol i iz i loh r bs i dd i ddsl i ddst i cvdd c in i ihe i ihl i ilr electrical characteristics dc characteristics (ta = ?0 to +75 c, vss = 0v reference) * 1 specifies rst pin only when the power-on reset circuit is selected with mask option. * 2 for rst pin, specifies the input current when pull-up resistor is selected, and specifies the leakage current when non-resistor is selected. * 3 when all output pins are left open. specifies only when the osd oscillation is halted. * 4 this device does not enter the stop mode. 1/2 frequency dividing clock operation v dd = 5.5v, 12mhz crystal oscillation (c 1 = c 2 = 15pf) v dd = 5.5v
? 13 cxp85840a/85848a/85856a 12.0 200 20 ac characteristics (1) clock timing * 1 indicates three values according to the contents of the clock control register (clc: 00fe h ) upper 2 bits (cpu clock selection). t sys (ns) = 2000/fc (upper 2 bits = ?0?, 4000/fc (upper 2 bits = ?1?, 16000/fc (upper 2 bits = ?1? 37.5 t sys * 1 + 50 system clock frequency system clock input pulse width system clock input rise and fall times event count input clock pulse width event count input clock rise and fall times f c t xl , t xh t cr , t cf t eh , t el t er , t ef xtal extal extal extal ec ec mhz ns ns ns ms item symbol pins conditions typ. max. unit fig. 1, fig. 2 fig. 1, fig. 2 external clock drive fig. 1, fig. 2 external clock drive fig. 3 fig. 3 (ta = ?0 to +75 c, v dd = 4.5 to 5.5v, vss = 0v reference) fig. 1. clock timing e x t a l t x h t x l t c f t c r 0 . 4 v v d d 0 . 4 v 1 / f c fig. 2. clock applied conditions a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a c r y s t a l o s c i l l a t i o n c e r a m i c o s c i l l a t i o n e x t a l x t a l e x t e r n a l c l o c k e x t a l x t a l o p e n c 1 c 2 fig. 3. event count clock timing e c t e h t e l t e f t e r 0 . 2 v d d 0 . 8 v d d min.
? 14 cxp85840a/85848a/85856a (2) serial transfer (ta = ?0 to +75 c, v dd = 4.5 to 5.5v, vss = 0v reference) item sck cycle time t kcy sck input mode output mode sck input mode sck output mode sck input mode sck output mode sck input mode sck output mode sck input mode sck output mode 1000 8000/fc 400 4000/fc ?50 100 200 200 100 200 100 ns ns ns ns ns ns ns ns ns ns sck si si so t kh t kl t sik t ksi t kso sck high and low level widths si input setup time (for sck - ) si hold time (for sck - ) sck ? so delay time symbol pins conditions min. max. unit note) the load of sck output mode and so output delay time is 50 pf + 1ttl. fig. 4. serial transfer timing 0 . 2 v d d 0 . 8 v d d t k l t k h s o t k c y t s i k t k s i 0 . 2 v d d 0 . 8 v d d t k s o 0 . 2 v d d 0 . 8 v d d o u t p u t d a t a i n p u t d a t a s i s c k
? 15 cxp85840a/85848a/85856a resolution linearity error zero transition voltage full-scale transition voltage conversion time sampling time analog input voltage v zt * 1 v ft * 2 t conv t samp v ian an0 to an5 ta = 25 c v dd = 5.0v vss = 0v ?0 4910 160/f adc * 3 12/f adc * 3 0 10 4970 8 3 70 5030 v dd bits lsb mv mv s s v item symbol pins conditions min. typ. max. unit (3) a/d converter (ta = ?0 to +75 c, v dd = 4.5 to 5.5v, vss = 0v reference ) l i n e a r i t y e r r o r v z t v f t a n a l o g i n p u t f f h f e h 0 1 h 0 0 h d i g i t a l c o n v e r s i o n v a l u e fig. 5. definitions of a/d converter terms 00 ( f = f ex /2) 01 ( f = f ex /4) 11 ( f = f ex /16) f adc = f c /2 f adc = f c /4 f adc = f c /16 f adc = f c cks pck1, 0 0 ( f /2 selection) 1 ( f selection) f adc = f c /2 f adc = f c /8 * 1 v zt : value at which the digital conversion value changes from 00 h to 01 h and vice versa. * 2 v ft : value at which the digital conversion value changes from fe h to ff h and vice versa. * 3 f adc indicates the below values due to the contents of bit 6 (cks) of the a/d control register (adc: 00f9 h ) and bits 7 (pck1) and 6 (pck0) of the clock control register (clc: 00fe h ).
? 16 cxp85840a/85848a/85856a external interruption high and low level widths reset input low level width int0 int1 int2 rst 1 32/fc s s item symbol pins conditions min. max. unit t ih t il t rsl t r t off v dd power-on reset repeated power-on reset 0.05 1 50 ms ms item symbol pins conditions min. max. unit (4) interruption, reset input (ta = ?0 to +75 c, v dd = 4.5 to 5.5v, vss = 0v reference) (5) power-on reset * 1 (ta = ?5 to +75 c, vss = 0v reference) 0 . 2 v d d 0 . 8 v d d t i h t i l i n t 0 i n t 1 i n t 2 ( f a l l i n g e d g e ) * 1 specifies only when the power-on reset function is selected. 0 . 2 v 0 . 2 v 4 . 5 v v d d t r t o f f t a k e c a r e w h e n t u r n i n g t h e p o w e r o n . fig. 6. interruption input timing t r s l 0 . 2 v d d r s t fig. 7. rst input timing fig. 8. power-on reset power supply rise time power supply cut-off time
? 17 cxp85840a/85848a/85856a (6) i 2 c bus timing (ta = ?0 to +75 c, v dd = 4.5 to 5.5v, vss = 0v reference ) item scl clock frequency bus-free time before starting transfer hold time for starting transfer clock low level width clock high level width setup time for repeated transfers data hold time data setup time sda, scl rise time sda, scl fall time setup time for transfer completion f slc t buf t hd; sta t low t high t su; sta t hd; dat t su; dat t r t f t su; sto scl sda, scl sda, scl scl scl sda, scl sda, scl sda, scl sda, scl sda, scl sda, scl 0 4.7 4.0 4.7 4.0 4.7 0 * 1 250 4.7 100 1 300 khz s s s s s s ns s ns s symbol pins conditions min. max. unit * 1 the data hold time should be 300ns or more because the scl rise time (300ns max.) is not included in it. fig. 9. i 2 c bus transfer timing p s t t s u ; s t o t s u ; s t a t h d ; s t a t s u ; d a t t h i g h t h d ; d a t t f t r t l o w t h d ; s t a s p t b u f s d a s c l fig. 10. i 2 c bus device recommended circuit i 2 c d e v i c e i 2 c d e v i c e r s r s r s r s r p r p s d a 0 ( o r s d a 1 ) s c l 0 ( o r s c l 1 ) a pull-up resistor (rp) must be connected to sda0 (or sda1) and scl0 (or scl1). the sda0 (or sda1) and scl0 (or scl1) series resistance (rs = 300 or less) can be used to reduce the spike noise caused by crt flashover.
? 18 cxp85840a/85848a/85856a (7) osd timing (ta = ?0 to +75 c, v dd = 4.5 to 5.5v, vss = 0v reference ) item osd clock frequency hsync pulse width vsync pulse width hsync after-write rise and fall times vsync before-write rise and fall times f osc t hwd t vwd t hcg t vcg exlc xlc hsync vsync hsync vsync fig. 12 fig. 11 fig. 11 fig. 11 fig. 11 4 1.2 1 16.5 200 1.0 mhz s h* ns s symbol pins conditions unit min. max. fig. 11. osd timing 0 . 8 v d d 0 . 2 v d d t h c g t h w d h s y n c f o r o s d i / o p o l a r i t y r e g i s t e r ( o p o l : 0 1 f d h ) b i t 7 a t 0 0 . 8 v d d 0 . 2 v d d t v c g v s y n c f o r o s d i / o p o l a r i t y r e g i s t e r ( o p o l : 0 1 f d h ) b i t 6 a t 0 t v w d fig. 12. lc oscillation circuit connection l c 2 c 1 e x l c x l c r * 1 * 1 the xlc series resistor can reduce the frequency of occurrence of the undesired radiation. * h indicates 1hsync period.
? 19 cxp85840a/85848a/85856a (8) data slicer external circuit (ta = ?0 to +75 c, v dd = 4.5 to 5.5v, vss = 0v reference ) item vin pin coupling capacitance cap pin capacitance pll low-pass filter capacitance composite video signal input c vin ccap c lpf video in vin cap lfc1, lfc2 vin 0.1 4700 0.47 2.0 f pf f vp-p symbol pin min. unit typ. max. fig. 13. data slicer external recommended circuit the b characteristics or more of temperature characteristics is recommended. the b characteristics or more of temperature characteristics is recommended. the b characteristics or more of temperature characteristics is recommended. remarks c v d d l f c 1 v i n c a p c v s s c c a p v i d e o i n c v i n r 1 c l p f 5 . 0 v c 1 r 2 l f c 2 [recommended constant] r 1 = 220 (error: 5%; allowable power dissipation: 1/8w or more) r 2 = 1m (error: 5%; allowable power dissipation: 1/8w or more) c 1 = 1200pf (ceramic), the b characteristics or more of temperature characteristics is recommended.
? 20 cxp85840a/85848a/85856a appendix fig. 14. spc 700 series recommended oscillation circuit c 2 c 1 a a a a a a a a a a a a a a a e x t a l x t a l r d a a a a a a a a a a a a a a a e x t a l x t a l r d ( i ) manufacture kinseki ltd. model hc-49/u03 hc-19/u (-s) fc (mhz) 12.0 12.0 5 5 0 * 1 c 1 (pf) c 2 (pf) rd ( ) circuit example (i) 15 15 0 * 1 (i) * 1 the xtal series resistor can reduce the effect of the noise caused by the electrostatic discharge. item content reset pin pull-up resistor power-on reset circuit non-existent non-existent existent existent mask option table river eletec co., ltd.
? 21 cxp85840a/85848a/85856a fig. 15. characteristic curves i d d s u p p l y c u r r e n t [ m a ] i d d v s . v d d ( f c = 1 2 m h z , t a = 2 5 c , t y p i c a l ) v d d s u p p l y v o l t a g e [ v ] 3 4 5 6 0 . 1 1 0 0 i d d v s . f c ( v d d = 5 v , t a = 2 5 c , t y p i c a l ) 1 0 1 i d d s u p p l y c u r r e n t [ m a ] 5 0 4 5 4 0 3 5 3 0 2 5 2 0 1 5 1 0 5 0 f c s y s t e m c l o c k [ m h z ] 1 6 1 2 8 4 p a r a m e t e r c u r v e f o r o s d o s c i l l a t i o n l v s . c ( t h e o r e t i c a l l y c a l c u l a t e d v a l u e ) 1 0 m h z 1 2 m h z 1 4 m h z 1 0 0 1 0 0 l i n d u c t a n c e [ h ] 5 0 1 0 0 c 1 , c 2 c a p a c i t a n c e [ p f ] 1 6 m h z s l e e p m o d e 1 / 1 6 d i v i d i n g m o d e 1 / 4 d i v i d i n g m o d e 1 / 2 d i v i d i n g m o d e s l e e p m o d e 1 / 1 6 d i v i d i n g m o d e 1 / 4 d i v i d i n g m o d e 1 / 2 d i v i d i n g m o d e f o s c = c = c 1 / / c 2 1 2 p l c
? 22 cxp85840a/85848a/85856a package outline unit: mm p a c k a g e s t r u c t u r e m o l d i n g c o m p o u n d l e a d t r e a t m e n t l e a d m a t e r i a l p a c k a g e w e i g h t s o n y c o d e e i a j c o d e j e d e c c o d e s d i p - 6 4 p - 0 1 4 2 a l l o y s o l d e r p l a t i n g e p o x y / p h e n o l r e s i n 6 4 p i n s d i p ( p l a s t i c ) 7 5 0 m i l s d i p 0 6 4 - p - 0 7 5 0 - a 5 7 . 6 0 . 1 + 0 . 4 6 4 3 3 1 3 2 1 . 7 7 8 1 9 . 0 5 1 7 . 1 0 . 1 + 0 . 3 0 t o 1 5 0 . 2 5 0 . 0 5 + 0 . 1 0 . 5 m i n 4 . 7 5 0 . 1 + 0 . 4 3 m i n 0 . 5 0 . 1 0 . 9 0 . 1 5 8 . 6 g s o n y c o d e e i a j c o d e j e d e c c o d e 2 3 . 9 0 . 4 2 0 . 0 0 . 1 0 . 4 0 . 1 + 0 . 1 5 1 4 . 0 0 . 1 1 1 9 2 0 3 2 3 3 5 1 5 2 6 4 0 . 1 5 0 . 0 5 + 0 . 1 2 . 7 5 0 . 1 5 1 6 . 3 0 . 1 0 . 0 5 + 0 . 2 0 . 8 0 . 2 m 0 . 1 2 0 . 1 5 + 0 . 4 1 7 . 9 0 . 4 + 0 . 4 + 0 . 3 5 6 4 p i n q f p ( p l a s t i c ) q f p 6 4 p l 0 1 q f p 0 6 4 p 1 4 2 0 p a c k a g e m a t e r i a l l e a d t r e a t m e n t l e a d m a t e r i a l p a c k a g e m a s s e p o x y r e s i n s o l d e r / p a l l a d i u m 4 2 / c o p p e r a l l o y p a c k a g e s t r u c t u r e p l a t i n g 1 . 5 g 1 . 0

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